Programmable logic devices such as field programmable gate arrays (FPGAs) allow a designer to avoid the expense of constructing an ASIC to implement a desired function. Rather than design an ASIC, a user may configure an off-the-shelf programmable logic device such as an FPGA to implement the desired function. However, as compared to the ASIC it replaces, an FPGA is a much more complex device because the FPGA must include the circuitry necessary to make it configurable. This additional circuitry is made up of active devices and interconnects. The active devices in particular will have a certain amount of leakage current that will not be present in a corresponding ASIC. Thus, an FPGA implementing a given function will have higher static power consumption than an equivalent ASIC implementing the same function.
The architecture of a typical FPGA may be better understood with reference to FIG. 1. In FIG. 1, an FPGA 100 includes a core 105 shaving an array of programmable logic blocks 110 (also referred to in the art as programmable logic cells, configurable logic blocks, programmable logic elements, or programmable logic regions). Each logic block 110 includes one or more look-up tables (LUTs) (not illustrated) that are configured by a user to implement a desired logical function. In addition, each logic block 110 will typically include one or more registers and often some additional logic circuitry which facilitates more compact implementations of commonly used functions such as ripple-carry. Core 105 also includes a routing structure 120 that couples signals to and from logic blocks 110. Because each logic block 110 can typically implement just a few logic gates, a logical function that a user desires to implement will often require the configuration of a fairly large number of logic blocks 110. Routing structure 120 must be quite complex to allow the necessary routing of signals from one logic block 110 to another across this fairly large number of logic blocks 110. Numerous junctions in routing structure 120 are configured with multiplexers or other switching structures and drivers to allow one conductor in routing structure 120 to couple to another conductor as desired. As a result, the core 105 consisting of the configurable routing structure 120 and the logic blocks 110 consumes a substantial amount of power, even when the FPGA 100 is idle, although considerably more can be consumed when switching. It will be appreciated, however, that static power consumption (of the core) becomes more appreciable as transistor dimensions are pushed into the deep submicron region. As transistor dimensions shrink, the operating voltages must be reduced with the net effect that leakage current increases, thereby causing static power consumption increases.
Should an FPGA be powered from a line power supply, this idle power consumption may be relatively inexpensive to supply. However, in a handheld or mobile application, a conventional FPGA will demand too much power during idle periods, limiting battery charge run time to unacceptably short periods. Thus, various power-saving measures have been adopted. For example, a “brute force” approach involves turning off all the external power supplies to an FPGA while the FPGA is in a standby state. If the FPGA does not have a non-volatile configuration memory, all configuration information will be lost as a result of such power shutoffs, thereby requiring reconfiguration of the device from an external serial E-PROM or FLASH device. Such a reconfiguration typically takes 100 ms or longer, which may be an unacceptable delay.
Accordingly, there is a need in the art for improved power-saving programmable logic device architectures.